Xilinx 1000BASE-X Manual do Utilizador descarregar pdf (Página 88)

88 www.xilinx.com Ethernet 1000BASE-X PCS/PMA or SGMII v9.1

UG155 March 24, 2008

Chapter 7: 1000BASE-X with RocketIO Transceivers

Virtex-4 FX Devices

Figure 7-6 illustrates sharing clock resources across multiple instantiations of the core

when using MGTs. Note that the example design, when using the Virtex-4 family, can be

generated to connect either a single instance of the core, or connect a pair of core instances

to the transceiver pair present in an MGT tile. Figure 7-6 shows two instantiations of the

block level, where each block contains a pair of cores, subsequently illustrating clock

sharing between four cores in total.

More cores can be added by continuing to instantiate extra block-level modules. Share

clocks only between the MGTs in a single column. For each column, use a single

brefclk_p and brefclk_n differential clock pair and connect this to a GT11CLK_MGT

primitive. The clock output from this primitive should be shared across all used RocketIO

tiles in the column. See the Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide (UG076)

for more information.

To provide the 125 MHz clock for all core instances, select a TXOUTCLK1 port from any

MGT. This can be routed onto global clock routing using a BUFG as illustrated, and shared

between all cores and MGTs in the column. Although not illustrated in Figure 7-6, dclk

(the clock used for the calibration blocks and for the Dynamic Reconfiguration Port (DRP)

of the MGTs) can also be shared.

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Xilinx 1000BASE-X Manual do Utilizador Página 88