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UG155 March 24, 2008

Core Interfaces

Table 2-7: Optional RocketIO Transceiver Interface Pinout

Signal Direction Description

mgt_rx_reset

1. When the core is used with a RocketIO transceiver, userclk2 is used as the 125 MHz reference clock

for the entire core.

Output Reset signal issued by the core to the RocketIO

transceiver receiver path. Connect to RXRESET signal

of RocketIO transceiver.

mgt_tx_reset

Output Reset signal issued by the core to the RocketIO

transceiver transmitter path. Connect to TXRESET

signal of RocketIO transceiver.

userclk Input Also connected to TXUSRCLK and RXUSRCLK of the

RocketIO transceiver. Clock domain is not applicable.

userclk2 Input Also connected to TXUSRCLK2 and RXUSRCLK2 of

the RocketIO transceiver. Clock domain is not

applicable.

dcm_locked Input A DCM may be used to derive userclk and userclk2.

This is implemented in the HDL design example

delivered with the core. The core will use this input to

hold the RocketIO transceiver in reset until the DCM

obtains lock. Clock domain is not applicable.

rxbufstatus[1:0]

Input Connect to RocketIO signal of the same name.

rxchariscomma