Xilinx 1000BASE-X Manual do Utilizador descarregar pdf (Página 165)

Ethernet 1000BASE-X PCS/PMA or SGMII v9.1 www.xilinx.com 165

UG155 March 24, 2008

Required Constraints

The following UCF syntax shows these constraints being applied.

#***********************************************************

# PCS/PMA Clock period Constraints: please do not relax *

#***********************************************************

NET "userclk2" TNM_NET = "userclk2";

TIMESPEC "TS_userclk2" = PERIOD "userclk2" 8 ns HIGH 50 %;

NET "dclk" TNM_NET = "dclk";

TIMESPEC "TS_dclk" = PERIOD "dclk" 20 ns HIGH 50 %;

Setting MGT Transceiver Attributes

The Virtex-4 MGT device has many attributes. These attributes are set directly from HDL

source code for the transceiver wrapper file delivered with the example design. These are

in the file transceiver.vhd (for VHDL design entry) or transciever.v (for Verilog

design entry). See the Ethernet 1000BASE-X PCS/PMA or SGMII Getting Started Guide for a

detailed description of the example design provided with the core.

This HDL transceiver wrapper file was initially created using Architecture Wizard. See the

Virtex-4 FPGA RocketIO Multi-Gigabit Transceiver User Guide (UG076) for a description of

available attributes.

MGT Placement Constraints

The following UCF syntax illustrates the MGT placement contraints for the example

design. Because Virtex-4 MGTs are always available in pairs, two MGTs are always

instantiated in the example design, even if one is inactive.

#***********************************************************

# Example Rocket I/O placement *

#***********************************************************

# Lock down the REFCLK pins:

NET brefclk_p LOC = F26;

NET brefclk_n LOC = G26;

# Lock down the GT11 pair and GT11 clock module

INST "core_wrapper/rocketio/GT11_1000X_A" LOC = GT11_X0Y5;

INST "core_wrapper/rocketio/GT11_1000X_B" LOC = GT11_X0Y4;

INST "GT11CLK_MGT_INST" LOC = GT11CLK_X0Y3;

# Lock down the RocketIO pins:

NET "rxp0" LOC = J26;

NET "rxn0" LOC = K26;

NET "txp0" LOC = M26;

NET "txn0" LOC = N26;

NET "rxp1" LOC = U26;

NET "rxn1" LOC = V26;

NET "txp1" LOC = P26;

NET "txn1" LOC = R26;

1 2 ... 160 161 162 163 164 165 166 167 168 169 170 ... 229 230

Comentários a estes Manuais

Sem comentários

Xilinx 1000BASE-X Manual do Utilizador Página 165

Comentários a estes Manuais

Manuais e produtos relacionados com Hardware Xilinx 1000BASE-X