Xilinx LOGICORE UG144 Manual do Utilizador descarregar pdf (Página 30)

30 www.xilinx.com 1-Gigabit Ethernet MAC v8.5 User Guide

UG144 April 24, 2009

Chapter 2: Core Architecture

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MDIO Interface

Table 2-9 describes the MDIO Interface signals. See “Using the MDIO interface,” on page

76.

Table 2-9: MDIO Interface Signal Pinout

Signal Direction

Clock

Domain

Description

mdc Output host_clk Management Clock: programmable

frequency derived from host_clk.

mdio_in

1. mdio_in, mdio_out and mdio_tri can be connected to a Tri-state buffer to create a bi-directional mdio

signal suitable for connection to an external PHY.

Input host_clk Input data signal for communication with

PHY configuration and status. Tie high if

unused.

mdio_out

Output host_clk Output data signal for communication

with PHY configuration and status.

mdio_tri

Output host_clk Tristate control for MDIO signals; 0 signals

that the value on mdio_out should be

asserted onto the MDIO bus.

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