Xilinx LogiCore PLB PCI Full Bridge Manual do Utilizador

0PLB PCI Full Bridge (v1.00a)DS508 March 21, 20060 0Product SpecificationDS508 March 21, 2006 www.xilinx.com 1Product Specification© 2005 Xilinx, Inc.

PLB PCI Full Bridge (v1.00a)10 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSG27IPIF BAR to which PCI BAR 0 is mappedC_PCIBAR2

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 11Product SpecificationEARLY ACCESSG40PCI2IPIF FIFO occupancy level in double words th

PLB PCI Full Bridge (v1.00a)12 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSG50Number of IDELAY controllers instantiated. Ignor

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 13Product SpecificationEARLY ACCESSG61Include configuration functionality via IPIF tra

PLB PCI Full Bridge (v1.00a)14 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSPLB PCI Bus Interface I/O SignalsThe I/O signals fo

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 15Product SpecificationEARLY ACCESSP27 Sl_rdBTerm PLB Bus OP28Sl_MBusy(0:C_PLB_NUM_MAS

PLB PCI Full Bridge (v1.00a)16 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSP55CBE[(C_PCI_DBUS_WIDTH/8)-1:0]PCI Bus I/O Time-mu

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 17Product SpecificationEARLY ACCESSThe REQ_N_toArb facilitates an interface to an inte

PLB PCI Full Bridge (v1.00a)18 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSPort and Parameter DependenciesThe dependencies bet

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 19Product SpecificationEARLY ACCESSG12 C_IPIFBAR2PCIBAR_2G1, G10, G11 and G48Meaningfu

PLB PCI Full Bridge (v1.00a)2 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSFeatures• Independent PLB and PCI clocks• 33 MHz, 32

PLB PCI Full Bridge (v1.00a)20 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSG26 C_PCIBAR_NUM G27-G32The set of PCI/v3.0 BAR-par

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 21Product SpecificationEARLY ACCESSG43C_NUM_PCI_RETRIES_IN_WRITESG44C_NUM_PCI_PRDS_BET

PLB PCI Full Bridge (v1.00a)22 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSSupported PCI Bus CommandsThe list of commands supp

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 23Product SpecificationEARLY ACCESSPLB PCI Bridge Register DescriptionsThe PLB PCI Bri

PLB PCI Full Bridge (v1.00a)24 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSRegister and Parameter DependenciesThe addressable

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 25Product SpecificationEARLY ACCESSGlobal Interrupt Enable Register DescriptionA globa

PLB PCI Full Bridge (v1.00a)26 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSBridge Interrupt Enable Register DescriptionThe PLB

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 27Product SpecificationEARLY ACCESSPLB PCI Bridge Reset Register DescriptionThe IP Res

PLB PCI Full Bridge (v1.00a)28 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSConfiguration Address Port Register DescriptionThe

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 29Product SpecificationEARLY ACCESSbus number. The highest subordinate bus number is a

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 3Product SpecificationEARLY ACCESSdefault in all transfers. Address translation is per

PLB PCI Full Bridge (v1.00a)30 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSThe example below shows how the IPIFBAR2PCIBAR_N re

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 31Product SpecificationEARLY ACCESSWriting 0xFEDC0000 to IPIFBAR2PCIBAR_1 High-Order B

PLB PCI Full Bridge (v1.00a)32 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSPLB PCI TransactionsThe following subsections discu

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 33Product SpecificationEARLY ACCESSFor all the transactions listed above, the followin

PLB PCI Full Bridge (v1.00a)34 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESS• Address translations in both directions are perfo

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 35Product SpecificationEARLY ACCESSmode). • If the PCI target address space is IO-spac

PLB PCI Full Bridge (v1.00a)36 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESS• If a SERR occurs during a valid data phase on a b

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 37Product SpecificationEARLY ACCESSTable 17 summarizes the abnormal conditions with wh

PLB PCI Full Bridge (v1.00a)38 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSwhen an incomplete PCI transactions occur or when P

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 39Product SpecificationEARLY ACCESSburst write data from the PLB to PCI beyond the val

PLB PCI Full Bridge (v1.00a)4 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSSystem ResetWhen the bridge is reset, both RST_N and

PLB PCI Full Bridge (v1.00a)40 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESStransaction. The PLB PCI Bridge performs retries up

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 41Product SpecificationEARLY ACCESSPCI Initiator Initiates a Read Request of a PLB Sla

PLB PCI Full Bridge (v1.00a)42 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSFurthermore, it is the responsibility of the PCI in

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 43Product SpecificationEARLY ACCESSIf the PLB clock is slower, the data flow is a seri

Ta bl e 1 9 : Response to PCI initiator doing a read of a remote PLB slave that terminates the transfer with an abnormal condition on PLB bus Abno

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 45Product SpecificationEARLY ACCESSnumber of double words are written, the IPIF master

PLB PCI Full Bridge (v1.00a)46 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSdefined number of retries are not successful, the P

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 47Product SpecificationEARLY ACCESSbridge is not used. As with Memory and IO data tran

Table 21: Results of v3.0 core Command Register configuration by remote host bridge (PCI-side) and by self-configuration (PLB-side)Results in Comman

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 49Product SpecificationEARLY ACCESSto the Configuration Data Port register initiates a

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 5Product SpecificationEARLY ACCESScore. These documents detail the v3.0 core operation

PLB PCI Full Bridge (v1.00a)50 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSsubordinate buses. Device numbers are independent f

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 51Product SpecificationEARLY ACCESSDesign DebugThe OBP PCI Bridge has a test vector ou

PLB PCI Full Bridge (v1.00a)52 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSThe constraints are also implemented automatically

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 53Product SpecificationEARLY ACCESSNET "*/RST_N" IOBDELAY = BOTH ;NET &q

PLB PCI Full Bridge (v1.00a)54 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESS#TIMEGRP "PCI_PADS_D" OFFSET=OUT 11.000 A

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 55Product SpecificationEARLY ACCESSone IDELAYCTRl without LOC constraints, the tools w

PLB PCI Full Bridge (v1.00a)56 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSThe parameter C_IDELAYCTRL_LOC has the syntax of ID

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 57Product SpecificationEARLY ACCESSthe ucf-file in the implementation directory of the

PLB PCI Full Bridge (v1.00a)58 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSReference DocumentsThe following documents contain

PLB PCI Full Bridge (v1.00a)6 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSExample 3 outlines the use of the PCIBAR parameter s

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 7Product SpecificationEARLY ACCESSAs in example 1, it is assumed that the parameter C_

PLB PCI Full Bridge (v1.00a)8 www.xilinx.com DS508 March 21, 2006Product SpecificationEARLY ACCESSAccessing the PLB PCI Bridge PCIBAR_1 with address 0

PLB PCI Full Bridge (v1.00a)DS508 March 21, 2006 www.xilinx.com 9Product SpecificationEARLY ACCESSG13IPIF BAR 2 memory designatorC_IPIF_SPACETYPE_20 =