Xilinx V2.1 Manual do Utilizador descarregar pdf (Página 35)

Basic Elements 35

Xilinx Blocks

Xilinx LogiCORE

The block always uses the Xilinx LogiCORE: Binary Counter V5.0.

The Core datasheet can be found on your local disk at:

%XILINX%\coregen\ip\xilinx\eip1\com\xilinx\ip\baseblox_v5_0\do

c\binary_counter.pdf

Delay

The Xilinx Delay block is a delay line (also called a shift register) of

conﬁgurable length, allowing you to add latency to your design. Data

presented at the input will appear at the output after a user speciﬁed

number of sample periods.

The Delayblock differs from theRegister in that the Register allowsonly

latency of 1, and contains an Initial Value parameter. The Delay block supports a user

speciﬁed latency, but no initial value, other than zeroes.

Block Parameters Dialog Box

The block parameters dialog box can be invoked by double-clicking the icon in your

Simulink model.

Figure 3-9: Delay block parameters dialog box

Parameters speciﬁc to this block are:

• Initialize with Zeros: The block’s internal registers are set to zero if this

option is selected, otherwise the output will be NaN (Not a Number) until the

registers are ﬂushed. For example, if the Delay block has a latency of 5 and this

option is selected, the ﬁrst ﬁve output values will be zeros. If this option is not

selected, the ﬁrst ﬁve output values will be NaN.

• Latency: You may set the amount of latency in the Latency ﬁeld.

Other parameters usedby thisblock areexplained in the CommonParameters section

of the previous chapter.

The Delay block does not use a Xilinx LogiCORE, but is efﬁciently mapped to utilize

the SRL16 feature of Xilinx devices.

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Xilinx V2.1 Manual do Utilizador Página 35