manuais Xilinx IP Ethernet AVB Endpoint v2.4 UG492

Manuais de instruções e guias do utilizador para Acessórios para Computador Xilinx IP Ethernet AVB Endpoint v2.4 UG492.
Disponibilizamos 1 manuais Xilinx IP Ethernet AVB Endpoint v2.4 UG492 em pdf para descarga gratuita: Manual do Utilizador

Xilinx IP Ethernet AVB Endpoint v2.4 UG492 Manual do Utilizador (172 páginas)

Marca: Xilinx | Categoria: Acessórios para Computador | Tamanho: 3.87 MB |

Índice

LogiCORE

Ethernet AVB

Endpoint v2.4

Revision History

Table of Contents

Chapter 5: Core Architecture

Chapter 13: Software Drivers

Kit (EDK)

Schedule of Figures

UG492 September 21, 2010

Schedule of Tables

About This Guide

Conventions

Online Document

List of Abbreviations

Preface: About This Guide

Recommended Design Experience

Additional Core Resources

Technical Support

Feedback

Document

Chapter 1: Introduction

Licensing the Core

Obtaining Your License Key

Installing the License File

Bridging

AVB Specifications

P802.1Qav

Typical Implementation

Component Name

Core Delivery Format

Ethernet AVB GUI Page 2

Output Generation

Core Architecture

EDK pcore Format

Functional Block Description

Tx Arbiter

Rx Splitter

MAC Header Filters

Tx PTP Packet Buffers

Tx Time Stamp

Rx PTP Packet Buffers

Rx Time Stamp

Tri-Mode Ethernet MACs

Core Interfaces

Legacy Traffic Interface

AV Traffic Interface

MAC Transmitter Interface

MAC Receiver Interface

MAC Management Interface

PLB Interface

Chapter 5: Core Architecture

Interrupt Signals

PTP Signals

Chapter 6

Tx AV Traffic I/F

Tx Arbiter Bandwidth Control

Chapter 7

Legacy MAC Header Filters

Match Pattern Register

Match Enable Register

VLAN Priority Match

Any Other Combinations

Rx AV Traffic I/F

Errored AV Traffic Reception

Chapter 8

,” which

RTC Implementation

(Step 2) Synchronized RTC

Time Stamping Logic

Chapter 9

Rx PTP Packet Buffer

Configuration and Status

Single Write Transaction

Rx Filtering Control Register

RTC Offset Control Registers

Current RTC Value Registers

RTC Interrupt Clear Register

Phase Adjustment Register

MAC Address Filter Registers

100

MAC MDIO Registers

101

Constraining the Core

103

signal:

104

Required Constraints

107

"rtc_regs_sample";

109

System Integration

111

Introduction

124

EDK Tool Domain

125

Ethernet

125

MHS File Syntax

127

AXI_Ethernet Configuration

130

Software Drivers

131

Clock Slave

132

Software System Integration

132

Core Initialization

134

Ethernet AVB Endpoint Setup

134

Quick Start Example Design

137

Generating the Core

139

Simulating the Example Design

141

What’s Next?

142

Chapter 15

143

Directory and File Contents

144

<component name>/doc

145

Table 15-9: Timing Directory

148

Implementation Scripts

151

Simulation Scripts

151

Example Design

152

Top-Level Example Design HDL

153

Ethernet Frame Stimulus

153

Ethernet Frame Checker

154

Loopback Module

154

PLB Module

155

Demonstration Test Bench

156

Customizing the Test Bench

157

X-Ref Target - Figure 15-3C

158

Development Kit (EDK)

165

RTC Time Stamp Accuracy

167

0 40 80 120 160 200 240RTC

168

RTC Sampling Error

169

Sampling

170

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